1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a multi-level metallization without a contact pad that allows large scale integration and a fabricating method thereof.
2. Discussion of Related Art
In the era of deep sub-micron, the integration rate of semiconductor devices grows higher in inverse proportion to their size. As the size of a conductive plug for connecting between devices and the space and width between metallization layers also become smaller, it is necessary to apply a multi-level metallization, W-plug, Al-reflow, and chemical mechanical polishing (CMP) processes to all semiconductor fabrications.
FIGS. 1a to 1e illustrates the process of fabricating a conventional semiconductor device having a multi-level metallization. As shown in FIG. 1a, a field oxide layer 12 is first formed on a device isolation region on a semiconductor substrate 10. The field oxide layer 12 defines an active area for an active device. Impurities are implanted into the substrate 10. The impurities diffuse forming an active area 14 in the substrate 10. A first insulating layer 16 is formed on the substrate 10 including the field oxide layer 12 and selectively etched to thereby expose a predetermined surface of the active area 14. The first and second contact hole h1 and h2, respectively, are formed on the etched part of the active area 14.
Referring to FIG. 1b, a conductive layer 18 on the first insulating layer 16 is formed.
Referring to FIG. 1c, the conductive layer 18 is subjected to a CMP or etch-back process until the surface of the first insulating layer 16 is exposed. The first and second conductive plugs 18a and 18b are formed in the first and second contact holes h1 and h2, respectively. A conductive layer is formed on the first insulating layer 16 including the conductive plugs 18a and 18b. The conductive layer is selectively etched to expose a predetermined surface of the first insulating layer 16 such that a first conductive layer pattern 20 connected to the first conductive plug 18a, a contact pad 22 connected to the second conductive plug 18b, and a second conductive layer pattern 24 are formed simultaneously. At this time, the first conductive pattern 20 connects the two upper/lower conductive plugs as well as serving as an electric metallization layer. The contact pad 22 connects the two upper/lower conductive plugs. The second conductive pattern 24 serves as an electric metallization wire.
The first conductive pattern 20, contact pad 22, and second conductive pattern 24 are spaced at a distance E preventing a short from developing between the patterns 20 and 24 and the pad 22. The spacer E is generally greater than about 0.4 xcexcm. The length of the spacer E depends on the resolution of the exposure equipment and the etching ability of the conductive layer consisting of the first and second conductive patterns 20 and 24 and contact pad 22.
Referring to FIG. 1d, a second insulating layer 26 is formed on the first insulating layer 16 and the first and second conductive layers 20 and 24 and contact pad 22. The second insulating layer 26 is selectively etched thereby exposing a predetermined surface of the first conductive layer 20 and contact pad 22. A third and fourth contact holes h3 and h4, respectively, are formed in the insulating layer 26.
The contact pad 22 is normally formed to be wider than the fourth contact hole h4. This is because light exposure during the photolithography process that forms the fourth contact hole h4 misaligns the fourth contact hole h4 to the contact pad 22. Thus, an inferior contact can occur between the contact pad 22 and the subsequently formed fourth conductive plug. To prevent this type of interior contact from forming, the contact pad 22 is currently fabricated with an overlap margin labeled as C in FIG. 1d. 
Referring to FIG. 1e, the third and fourth conductive plugs 28a and 28b are formed in the third and fourth contact holes h3 and h4, respectively, using the same method as described for forming the first and second contact holes h1 and h2, respectively. A third conductive pattern 30 connected to the third conductive plug 28a and the fourth conductive pattern 32 connected to the fourth conductive plug 28b are formed simultaneously by selectively etching a conductive layer deposited on the surface of the second insulating layer. The third and fourth conductive pattern, 30 and 32, respectively, serve as an electric metallization wire.
To summarize, the first insulating layer is formed on the semiconductor substrate 10 having the active area 14. The first and second contact holes h1 and h2 are formed on and passing through the first insulating layer 16 thereby exposing a predetermined surface of the active area 14. The first and second conductive plugs 18a and 18b are formed in the first and second contact holes h1 and h2, respectively. The contact pad 22 is connected to the second conductive plug 18b and interposed between the first conductive pattern 20, and the second conductive pattern 24. Each of the first and second conductive patterns 20 and 24, respectively, are spaced predetermined distance apart. The second insulating layer 26 is formed on the first insulating layer 16. The third and fourth contact holes h3 and h4 are formed passing through the second insulating layer 26 to thereby expose a predetermined surface of the first conductive pattern 20 and contact pad 22. The third and fourth conductive plugs 28a and 28b are formed in the third and fourth contact holes h3 and h4, respectively. The third conductive pattern 30 is connected to the third conductive plug 28a and the fourth conductive pattern 32 is connected to the fourth conductive plug 28b. The third and fourth conductive patterns 30 and 32 are spaced a predetermined distance apart.
Assuming that the horizontal width of the fourth conductive plug 28b is A, and the spacer between the first and second conductive patterns 20 and 24 and contact pad 22 is E, the horizontal and vertical width of the contact pad is A+(2*C) and the fourth contact hole h4 maintains a space greater than (C+E) to the first conductive pattern 20. In addition, the horizontal length between the first and second conductive patterns 20 and 24 on the same line is A+(2*C)+(2*E).
FIG. 2 is a top view of the layout structure of the conventional semiconductor device shown in FIG. 1e. Only the layout structure under the third and fourth conductive patterns 30 and 32, respectively, directly associated with the invention is shown in FIG. 2.
Referring to FIG. 2, the first conductive pattern 20, contact pad 22, and second conductive pattern 24 are spaced at a predetermined distance on the same line, having the contact pad 22 interposed. The second and fourth conductive plugs 18b and 28b are laid on/under the contact pad 22, and are connected to each other.
The following problems may occur when a semiconductor device is manufactured using the process described above. When forming the contact pad 22 to electrically connect the second conductive plug 18b and the fourth conductive plug 28b, the size of the contact pad 22 is structured to include the overlap margin C to prevent misalignment. The size of the overlap margin makes it impossible to reduce the width of the contact pad 22 not to exceed A+(2*C). The horizontal distance between the first and second conductive patterns 20 and 24 is actually larger than A+(2*C)+(2*E).
Limiting reduction of the pattern size in the horizontal direction in the semiconductor device makes large-scale integration of the device difficult if not impossible. Therefore, more effort is necessary to solve this problem. Accordingly, a need remains for an improved semiconductor device with a multi-level metallization.
An object of the present invention is to overcome the problems associated with prior art semiconductor devices.
Another object of the present invention is to provide a semiconductor device having a multi-level metallization capable of reducing the pattern size in a horizontal direction of the semiconductor device. The pattern size is reduced by changing the layout to have a structure where a second lower conductive plug and a fourth upper conductive plug are connected directly without a contact pad allowing large scale integration of the semiconductor device.
Yet another object of the present invention is to provide a method of effectively fabricating a semiconductor device having a multi-level metallization.
To achieve these and other objects of the present invention, a first embodiment semiconductor device having a multi-level metallization is provided. The semiconductor device includes a semiconductor substrate having an active area; a first insulating layer deposited on the substrate; first and second contact holes formed penetrating the first insulating layer exposing a predetermined surface of the active area; first and second conductive plugs respectively formed on the first and second contact holes; first and second conductive patterns spaced a predetermined distance apart on either side of the second conductive plug, the first conductive pattern being connected to the first conductive plug; an etching prevention layer and a second insulating layer sequentially formed on the first and second conductive patterns and the first insulating layer; a third contact hole formed penetrating the second insulating layer and the etching prevention layer exposing a predetermined surface of the first conductive pattern; a fourth contact hole formed penetrating the second insulating layer and the etching prevention layer exposing the second conductive plug; third and fourth conductive plugs respectively formed on the third and fourth contact holes; and third and fourth conductive patterns formed on predetermined surfaces of the second insulating layer, the third and fourth conductive patterns being respectively connected to the third and fourth conductive plugs.
A second embodiment of the semiconductor memory device of the present invention is also provided. The second embodiment of the semiconductor memory device includes a semiconductor substrate having an active area; a first insulating layer, an etching prevention layer, and a second insulating layer sequentially formed on the substrate; first and second contact holes formed penetrating the second insulating layer, the etching prevention layer, and the first insulating layer exposing a predetermined surface of the active area; first and second conductive plugs respectively formed in the first and second contact holes; first and second conductive pattern spaced a predetermined distance apart on either side of the second conductive plug, the first and second conductive patterns being formed on the second insulating layer and the first conductive pattern being connected to the first conductive plug; a third insulating layer formed on the first and second patterns and the second insulating layer; a third contact hole formed penetrating the third insulating layer exposing a predetermined surface of the first conductive pattern; a fourth contact hole formed penetrating the third insulating layer and the second insulating layer exposing the second conductive plug and a predetermined adjacent surface of the etching prevention layer; third and fourth conductive plugs respectively formed on the third and fourth contact holes; and third and fourth conductive patterns formed on predetermined surfaces of the second insulating layer, the third and fourth conductive patterns being respectively connected to the third and fourth conductive plugs.
A method of fabricating the first embodiment semiconductor memory device is also provided. The method comprises forming a first insulating layer on a semiconductor substrate having an active area; forming first and second contact holes by selectively etching the first insulating layer; forming first and second conductive plugs in the first and second contact holes, respectively; forming a conductive layer on the first insulating layer and the first and second conductive plugs; forming first and second conductive patterns on both sides of the second conductive plug by selectively etching the conductive layer thereby exposing the second conductive plug and a predetermined surface of the first insulating layer, the first conductive pattern being connected to the first conductive plug; sequentially forming an etching prevention layer and a second insulating layer on the first insulating layer, the first and second conductive patterns, and the second conductive plug; forming a third and fourth contact holes by selectively etching the second insulating layer and the etching prevention layer thereby exposing a predetermined surface of the first conductive pattern and the surface of the second conductive plug; forming third and fourth conductive plugs in the third and fourth contact holes, respectively; and forming a third and a fourth conductive patterns by forming a conductive layer on the second insulating later and the third and fourth plugs and selectively etching the conductive layer, the third conductive pattern being connected to the third conductive plug and the fourth conductive pattern being connected to the fourth conductive plug.
A method of fabricating the second embodiment semiconductor memory device is also provided. The method comprises sequentially forming a first insulating layer, an etching prevention layer, and a second insulating layer on a semiconductor substrate having an active area; forming a first and second contact holes by selectively etching the second insulating layer, the etching prevention layer, and first insulating layer; forming first and second conductive plugs in the first and second contact holes, respectively; forming a first conductive layer on the second insulating layer and the first and second conductive plugs; forming first and second conductive patterns on both sides of the second conductive plug by selectively etching the first conductive layer thereby exposing the second conductive plug and a predetermined surface of the second insulating layer, the first conductive pattern being connected to the first conductive plug; forming a third insulating layer on the second insulating layer, the first and second conductive patterns, and the second conductive plug; forming third and fourth contact holes by selectively etching the second and third insulating layers thereby exposing a predetermined surface of the first conductive pattern and a predetermined surface of the etching prevention layer adjacent to the second conductive plug; forming third and fourth conductive plugs in the third and fourth contact holes, respectively; forming a second conductive layer on the third insulating layer and the third and fourth conductive plugs; and forming third and fourth conductive patterns by selectively etching the second conductive layer, the third conductive pattern being connected to the third conductive plug and the fourth conductive pattern being connected to the fourth conductive plug.
If the semiconductor device having a multi-level metallization of the invention is fabricated to have the above-mentioned structure, the second conductive plug and the fourth conductive plug are connected directly to each other without a contact pad thereby reducing the horizontal length between the first and second conductive patterns.